ASAP: Accelerated Short-Read Alignment on Programmable Hardware

TL;DR

This paper introduces ASAP, a hardware accelerator on FPGA that dramatically speeds up short-read genome sequence alignment by leveraging circuit delay properties, achieving significant performance and energy efficiency improvements.

Contribution

The paper presents the ASAP FPGA-based accelerator for edit-distance computation, achieving over 200x speedup and 3760x energy efficiency gains compared to CPU implementations.

Findings

200x faster than CPU kernel implementation

2.2x faster for end-to-end alignment

3760x improvement in performance/Watt

Abstract

The proliferation of high-throughput sequencing machines ensures rapid generation of up to billions of short nucleotide fragments in a short period of time. This massive amount of sequence data can quickly overwhelm today's storage and compute infrastructure. This paper explores the use of hardware acceleration to significantly improve the runtime of short-read alignment, a crucial step in preprocessing sequenced genomes. We focus on the Levenshtein distance (edit-distance) computation kernel and propose the ASAP accelerator, which utilizes the intrinsic delay of circuits for edit-distance computation elements as a proxy for computation. Our design is implemented on an Xilinx Virtex 7 FPGA in an IBM POWER8 system that uses the CAPI interface for cache coherence across the CPU and FPGA. Our design is $200\times$ faster than the equivalent C implementation of the kernel running on the host processor and $2.2\times$ faster for an end-to-end alignment tool for 120-150 base-pair short-read sequences. Further the design represents a $3760\times$ improvement over the CPU in performance/Watt terms.