Low-Complexity Concatenated LDPC-Staircase Codes

TL;DR

This paper introduces a low-complexity concatenated LDPC-staircase coding scheme optimized for reduced decoding complexity, achieving significant gains with simplified hardware implementation and a favorable trade-off between SNR and complexity.

Contribution

It proposes a novel concatenated coding scheme with optimized degree distribution, including leaving some bits uncoded, and demonstrates substantial complexity reduction while maintaining coding gains.

Findings

Achieves up to 71% reduction in decoding complexity.

Provides a hardware-friendly quasi-cyclic code construction.

Shows a Pareto frontier characterizing SNR versus complexity trade-offs.

Abstract

A low-complexity soft-decision concatenated FEC scheme, consisting of an inner LDPC code and an outer staircase code is proposed. The inner code is tasked with reducing the bit error probability below the outer-code threshold. The concatenated code is obtained by optimizing the degree distribution of the inner-code ensemble to minimize estimated data-flow, for various choices of outer staircase codes. A key feature that emerges from this optimization is that it pays to leave some inner codeword bits completely uncoded, thereby greatly reducing a significant portion of the decoding complexity. The trade-off between required SNR and decoding complexity of the designed codes is characterized by a Pareto frontier. Computer simulations of the resulting codes reveals that the net coding-gains of existing designs can be achieved with up to 71\% reduction in complexity. A hardware-friendly quasi-cyclic construction is given for the inner codes, which can realize an energy-efficient decoder implementation, and even further complexity reductions via a layered message-passing decoder schedule.