Precursors of gate oxide degradation in SiC power MOSFETs

TL;DR

This paper demonstrates that gate oxide degradation precursors used in Si MOSFETs are also applicable to SiC MOSFETs, with experimental validation showing their increasing trends during stress, impacting device performance.

Contribution

It extends the understanding of gate oxide degradation precursors from Si to SiC MOSFETs and correlates their variations analytically and experimentally.

Findings

Precursors like threshold voltage, gate plateau voltage, and gate plateau time increase during degradation.

All three precursors exhibit a simultaneous increasing trend during stress.

Degradation precursors impact on-state and switching losses in SiC MOSFETs.

Abstract

Gate oxide degradation is more critical in Silicon-Carbide (SiC) MOSFETs than in Silicon (Si) MOSFETs. This is because of the smaller gate oxide thickness and the higher electric field that develops across the gate oxide in SiC MOSFETs. While multiple precursors have been identified for monitoring the gate oxide degradation in Si MOSFETs, very few precursors have been identified for SiC MOSFETs. The purpose of this paper is to demonstrate that gate oxide degradation precursors used in Si MOSFETs: a) threshold voltage, b) gate plateau voltage and c) gate plateau time, can also be used as precursors for SiC MOSFETS. Moreover, all three precursors are found to exhibit a simultaneous increasing trend (during the stress time) leading to an increase in on-state loss, switching loss and switching time of the SiC MOSFET. The existing studies of gate oxide degradation mechanisms in SiC MOSFETs, and their effects on threshold voltage and mobility were extended to correlate a variation of all three precursors using analytical expressions. The increasing trends of precursors were experimentally confirmed by inducing gate oxide degradation in commercial SiC MOSFET samples.