Level Zero Trigger Processor for the NA62 experiment
Dario Soldi, Stefano Chiozzi

TL;DR
The paper presents a novel fully digital Level Zero Trigger Processor for the NA62 experiment, capable of real-time event selection at high data rates using programmable logic and Ethernet communication.
Contribution
It introduces a new architecture for the L0 trigger system based on FPGA and Ethernet, enhancing real-time processing and synchronization in high-energy physics experiments.
Findings
Maximum latency of 1 ms achieved
Input rate of 10 MHz per sub-detector handled
Output trigger rate up to 1 MHz supported
Abstract
The NA62 experiment is designed to measure the ultra-rare decay branching ratio with a precision of at the CERN Super Proton Synchrotron (SPS). The trigger system of NA62 consists in three different levels designed to select events of physics interest in a high beam rate environment. The L0 Trigger Processor (L0TP) is the lowest level system of the trigger chain. It is hardware implemented using programmable logic. The architecture of the NA62 L0TP system is a new approach compared to existing systems used in high-energy physics experiments. It is fully digital, based on a standard gigabit Ethernet communication between detectors and the L0TP Board. The L0TP Board is a commercial development board, mounting a programmable logic device (FPGA). The primitives generated by sub-detectors are sent asynchronously using the UDP protocol to the…
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