High Speed SRT Divider for Intelligent Embedded System

TL;DR

This paper presents a highly parallel, pipelined radix-4 SRT division algorithm optimized for embedded systems, utilizing fuzzy logic to reduce delay and improve accuracy, achieving 281ns execution time on FPGA.

Contribution

It introduces a novel parallel pipelined radix-4 SRT divider using fuzzy logic for quotient selection, significantly reducing execution time in embedded applications.

Findings

Achieved 281ns division time for 64-bit floating point numbers.

Reduced critical path delay through parallel execution and fuzzy logic.

Successfully implemented on Xilinx FPGA with high efficiency.

Abstract

Increasing development in embedded systems, VLSI and processor design have given rise to increased demands from the system in terms of power, speed, area, throughput etc. Most of the sophisticated embedded system applications consist of processors, which now need an arithmetic unit with the ability to execute complex division operations with maximum efficiency. Hence the speed of the arithmetic unit is critically dependent on division operation. Most of the dividers use the SRT division algorithm for division. In IoT and other embedded applications, typically radix 2 and radix 4 division algorithms are used. The proposed algorithm lies on parallel execution of various steps so as to reduce time critical path, use fuzzy logic to solve the overlap problem in quotient selection, hence reducing maximum delay and increasing the accuracy. Every logical circuit has a maximum delay on which the timing of the circuit is dependent and the path, causing the maximum delay is known as the critical path. Our approach uses the previous SRT algorithm methods to make a highly parallel pipelined design and use Mamdani model to determine a solution to the overlapping problem to reduce the overall execution time of radix 4 SRT division on 64 bits double precision floating point numbers to 281ns. The design is made using Bluespec System Verilog, synthesized and simulated using Vivado v.2016.1 and implemented on Xilinx Virtex UltraScale FPGA board.