Selecting Microarchitecture Configuration of Processors for Internet of Things

TL;DR

This paper introduces a fast design space exploration method for optimizing processor microarchitecture configurations tailored for IoT devices, balancing power and performance efficiently.

Contribution

It presents a novel, efficient methodology for microarchitecture configuration selection that significantly reduces exploration time while maintaining near-optimal results for IoT processors.

Findings

Achieves configurations within 2.23%-3.69% of exhaustive search results.

Explores only 3%-5% of the design space.

Provides 24.16x speedup in exploration time.

Abstract

The Internet of Things (IoT) makes use of ubiquitous internet connectivity to form a network of everyday physical objects for purposes of automation, remote data sensing and centralized management/control. IoT objects need to be embedded with processing capabilities to fulfill these services. The design of processing units for IoT objects is constrained by various stringent requirements, such as performance, power, thermal dissipation etc. In order to meet these diverse requirements, a multitude of processor design parameters need to be tuned accordingly. In this paper, we propose a temporally efficient design space exploration methodology which determines power and performance optimized microarchitecture configurations. We also discuss the possible combinations of these microarchitecture configurations to form an effective two-tiered heterogeneous processor for IoT applications. We evaluate our design space exploration methodology using a cycle-accurate simulator (ESESC) and a standard set of PARSEC and SPLASH2 benchmarks. The results show that our methodology determines microarchitecture configurations which are within 2.23%-3.69% of the configurations obtained from fully exhaustive exploration while only exploring 3%-5% of the design space. Our methodology achieves on average 24.16x speedup in design space exploration as compared to fully exhaustive exploration in finding power and performance optimized microarchitecture configurations for processors.