VIBNN: Hardware Acceleration of Bayesian Neural Networks
Ruizhe Cai, Ao Ren, Ning Liu, Caiwen Ding, Luhao Wang, Xuehai Qian,, Massoud Pedram, Yanzhi Wang

TL;DR
This paper presents VIBNN, an FPGA-based hardware accelerator for Bayesian Neural Networks that efficiently handles Gaussian random number generation, enabling high throughput and energy efficiency in variational inference tasks.
Contribution
Introduction of two high-performance Gaussian random number generators and a scalable FPGA architecture for accelerating Bayesian Neural Networks.
Findings
Achieves 321,543.4 images/sec throughput.
Energy efficiency of up to 52,694.8 images/J.
Maintains similar accuracy to software implementations.
Abstract
Bayesian Neural Networks (BNNs) have been proposed to address the problem of model uncertainty in training and inference. By introducing weights associated with conditioned probability distributions, BNNs are capable of resolving the overfitting issue commonly seen in conventional neural networks and allow for small-data training, through the variational inference process. Frequent usage of Gaussian random variables in this process requires a properly optimized Gaussian Random Number Generator (GRNG). The high hardware cost of conventional GRNG makes the hardware implementation of BNNs challenging. In this paper, we propose VIBNN, an FPGA-based hardware accelerator design for variational inference on BNNs. We explore the design space for massive amount of Gaussian variable sampling tasks in BNNs. Specifically, we introduce two high performance Gaussian (pseudo) random number…
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