Comments on "Dual-rail asynchronous logic multi-level implementation"
P Balasubramanian
TL;DR
This paper critically discusses the challenges and clarifies key concepts related to dual-rail asynchronous logic multi-level implementation, focusing on delay-insensitivity and physical realization issues.
Contribution
It offers detailed clarifications and identifies problematic issues in the existing approach to dual-rail asynchronous logic multi-level implementation.
Findings
Highlights issues with delay-insensitivity assumptions
Clarifies concepts of robust asynchronous logic
Discusses physical implementation challenges
Abstract
In this research communication, we comment on "Dual-rail asynchronous logic multi-level implementation" [Integration, the VLSI Journal 47 (2014) 148-159] by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multi-level decomposition, and physical implementation.
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