Voltage-driven Building Block for Hardware Belief Networks

TL;DR

This paper introduces a voltage-driven hardware building block for probabilistic spin logic, enabling the implementation of complex probabilistic computations like the Subset Sum Problem directly in hardware.

Contribution

It presents a novel hardware building block based on embedded MTJs and capacitive voltage adders, facilitating scalable probabilistic neural network architectures.

Findings

Hardware implementation of weighted p-bits demonstrated via SPICE simulations.

Successfully solved a small NP-complete problem in hardware.

Showcased potential for scalable probabilistic computing architectures.

Abstract

Probabilistic spin logic (PSL), based on networks of binary stochastic neurons (or p-bits), has been shown to provide a viable framework for many functionalities including Ising computing, Bayesian inference, invertible Boolean logic and image recognition. This paper presents a hardware building block for the PSL architecture, consisting of an embedded MTJ and a capacitive voltage adder of the type used in neuMOS. We use SPICE simulations to show how identical copies of these building blocks (or weighted p-bits) can be interconnected with wires to design and solve a small instance of the NP-complete Subset Sum Problem fully in hardware.