Modeling and Simulation of Electromigration Behavior for Via Array Structure
Karthik Airani, Rohit Guttal

TL;DR
This paper presents an analytical model and algorithm to predict electromigration lifetime in via array structures, accounting for uneven current distribution and stress effects, validated by experimental data.
Contribution
It introduces a novel stress time translation formula and cumulative failure distribution equation for modeling electromigration in via arrays, improving lifetime prediction accuracy.
Findings
Model accurately predicts electromigration lifetime distribution trends.
Proposed method correlates well with experimental results.
Accounts for memory effects and uneven current distribution.
Abstract
In this paper, we develop a analytical model and algorithm for calculating uneven current distribution in via array structures. We propose a stress time translation formula and cumulative failure distribution equation to model the memory effect of electro migration stress or damage on a via array structure. We develop a method to project via array electromigration (EM) lifetime based on an arbitrary via failure sequence, and demonstrate that the proposed via array EM lifetime distribution trend correlates well with experimental results.
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Taxonomy
TopicsCopper Interconnects and Reliability · Electronic Packaging and Soldering Technologies · Semiconductor materials and devices
