A generative modeling approach for benchmarking and training shallow quantum circuits

TL;DR

This paper introduces a quantum circuit learning algorithm for benchmarking and training shallow quantum circuits, demonstrating its effectiveness in state preparation, generating thermal states, and proposing a new hardware-independent metric called the qBAS score.

Contribution

The paper presents a novel quantum circuit learning approach tailored for near-term quantum devices, including a new benchmarking metric and experimental validation.

Findings

Successfully learned GHZ states and thermal states using the proposed method.

Introduced the qBAS score as a hardware-independent benchmarking metric.

Experimental evaluation on an ion-trap quantum computer showing trade-offs in circuit design.

Abstract

Hybrid quantum-classical algorithms provide ways to use noisy intermediate-scale quantum computers for practical applications. Expanding the portfolio of such techniques, we propose a quantum circuit learning algorithm that can be used to assist the characterization of quantum devices and to train shallow circuits for generative tasks. The procedure leverages quantum hardware capabilities to its fullest extent by using native gates and their qubit connectivity. We demonstrate that our approach can learn an optimal preparation of the Greenberger-Horne-Zeilinger states, also known as "cat states". We further demonstrate that our approach can efficiently prepare approximate representations of coherent thermal states, wave functions that encode Boltzmann probabilities in their amplitudes. Finally, complementing proposals to characterize the power or usefulness of near-term quantum devices, such as IBM's quantum volume, we provide a new hardware-independent metric called the qBAS score. It is based on the performance yield in a specific sampling task on one of the canonical machine learning data sets known as Bars and Stripes. We show how entanglement is a key ingredient in encoding the patterns of this data set; an ideal benchmark for testing hardware starting at four qubits and up. We provide experimental results and evaluation of this metric to probe the trade off between several architectural circuit designs and circuit depths on an ion-trap quantum computer.