Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs
Khaza Anuarul Hoque, Otmane Ait Mohamed, Yvon Savaria

TL;DR
This paper introduces a probabilistic model checking approach to analyze and optimize TMR partitioning in SRAM-based FPGAs for aerospace, considering multiple upset scenarios and early design stage decisions.
Contribution
It presents a formal methodology using Markov models and PRISM to evaluate reliability and determine optimal TMR partitioning early in FPGA design.
Findings
Model captures single and multiple-cell upsets.
Optimal number of TMR partitions can be identified early.
Reliability improves with appropriate partitioning and scrub rate.
Abstract
SRAM-based FPGAs are popular in the aerospace industry for their field programmability and low cost. However, they suffer from cosmic radiation-induced Single Event Upsets (SEUs). Triple Modular Redundancy (TMR) is a well-known technique to mitigate SEUs in FPGAs that is often used with another SEU mitigation technique known as configuration scrubbing. Traditional TMR provides protection against a single fault at a time, while partitioned TMR provides improved reliability and availability. In this paper, we present a methodology to analyze TMR partitioning at early design stage using probabilistic model checking. The proposed formal model can capture both single and multiple-cell upset scenarios, regardless of any assumption of equal partition sizes. Starting with a high-level description of a design, a Markov model is constructed from the Data Flow Graph (DFG) using a specified number…
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