PACER: Peripheral Activity Completion Estimation and Recognition

TL;DR

PACER introduces algorithms to detect peripheral activity completion in real-time, enabling energy savings up to 80% and latency reductions up to 67% by exploiting slack between worst-case estimates and actual response times.

Contribution

This paper presents a novel suite of algorithms for real-time peripheral activity completion detection, improving energy efficiency and latency in embedded systems.

Findings

Energy expenditure reduced by up to 80%

Latency reduced by up to 67%

Effective in conjunction with IODVS across multiple devices

Abstract

Embedded peripheral devices such as memories, sensors and communications interfaces are used to perform a function external to a host microcontroller. The device manufacturer typically specifies worst-case current consumption and latency estimates for each of these peripheral actions. Peripheral Activity Completion, Estimation and Recognition (PACER) is introduced as a suite of algorithms that can be applied to detect completed peripheral operations in real-time. By detecting activity completion, PACER enables the host to exploit slack between the worst-case estimate and the actual response time. These methods were tested independently and in conjunction with IODVS on multiple common peripheral devices. For the peripheral devices under test, the test fixture confirmed decreases in energy expenditures of up to 80% and latency reductions of up to 67%.