A Software-defined SoC Memory Bus Bridge Architecture for Disaggregated Computing
Dimitris Syrivelis, Andrea Reale, Kostas Katrinis, Christian Pinto

TL;DR
This paper introduces a software-defined memory bus bridge architecture for disaggregated computing, enabling flexible, high-performance communication across multiple chips and boards, and supporting datacenter resource management.
Contribution
It presents a novel, configurable memory bus bridge architecture that facilitates scalable, disaggregated resource sharing in multiprocessor SoCs with a prototype implementation.
Findings
Supports communication between hundreds of masters and slaves
Enables runtime configuration for resource management
Demonstrates application-level performance in prototype
Abstract
Disaggregation and rack-scale systems have the potential of drastically decreasing TCO and increasing utilization of cloud datacenters, while maintaining performance. While the concept of organising resources in separate pools and interconnecting them together on demand is straightforward, its materialisation can be radically different in terms of performance and scale potential. In this paper, we present a memory bus bridge architecture which enables communication between 100s of masters and slaves in todays complex multiprocessor SoCs, that are physically intregrated in different chips and even different mainboards. The bridge tightly couples serial transceivers and a circuit network for chip-to-chip transfers. A key property of the proposed bridge architecture is that it is software-defined and thus can be configured at runtime, via a software control plane, to prepare and steer…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
