Design Exploration of Hybrid CMOS-OxRAM Deep Generative Architectures

TL;DR

This paper introduces hybrid CMOS-OxRAM deep generative models using HfOx devices for various neural functions, validated through simulations on digit classification and reconstruction with promising accuracy and endurance.

Contribution

It presents a novel hybrid CMOS-OxRAM architecture for deep generative models, demonstrating effective training and high accuracy without backpropagation.

Findings

Achieved 95.5% accuracy on MNIST digit classification.

MSE of 0.003 for the autoencoder surpassing software models.

Endurance of ~7000 switching cycles per OxRAM device.

Abstract

Deep Learning and its applications have gained tremendous interest recently in both academia and industry. Restricted Boltzmann Machines (RBMs) offer a key methodology to implement deep learning paradigms. This paper presents a novel approach for realizing hybrid CMOS-OxRAM based deep generative models (DGM). In our proposed hybrid DGM architectures, HfOx based (filamentary-type switching) OxRAM devices are extensively used for realizing multiple computational and non-computational functions such as: (i) Synapses (weights), (ii) internal neuron-state storage, (iii) stochastic neuron activation and (iv) programmable signal normalization. To validate the proposed scheme we have simulated two different architectures: (i) Deep Belief Network (DBN) and (ii) Stacked Denoising Autoencoder for classification and reconstruction of hand-written digits from a reduced MNIST dataset of 6000 images. Contrastive-divergence (CD) specially optimized for OxRAM devices was used to drive the synaptic weight update mechanism of each layer in the network. Overall learning rule was based on greedy-layer wise learning with no back propagation which allows the network to be trained to a good pre-training stage. Performance of the simulated hybrid CMOS-RRAM DGM model matches closely with software based model for a 2-layers deep network. Top-3 test accuracy achieved by the DBN was 95.5%. MSE of the SDA network was 0.003, lower than software based approach. Endurance analysis of the simulated architectures show that for 200 epochs of training (single RBM layer), maximum switching events/per OxRAM device was ~ 7000 cycles.