High Performance Architecture for Flow-Table Lookup in SDN on FPGA

TL;DR

This paper introduces RTST, a high-performance, memory-efficient FPGA architecture for flow-table lookup in SDN, achieving high throughput and supporting dynamic updates.

Contribution

The paper presents RTST, a novel range-based ternary search tree with a parallel multi-pipeline FPGA implementation for efficient SDN flow-lookup.

Findings

Achieves 670 MPPS throughput on FPGA.

Uses only 1 byte of memory per byte of flow.

Supports dynamic updates efficiently.

Abstract

We propose Range-based Ternary Search Tree (RTST), a tree-based approach for flow-table lookup in SDN network. RTST builds upon flow-tables in SDN switches to provide a fast lookup among flows. We present a parallel multi-pipeline architecture for implementing RTST that benefits from high throughput and low latency. The proposed RTST and architecture achieve a memory efficiency of 1 byte of memory for each byte of flow. We also present a set of techniques to support dynamic updates. Experimental results show that RTST can be used to improve the performance of flow-lookup. It achieves a throughput of 670 Million Packets Per Second (MPPS), for a 1 K 15-tuple flow-table, on a state-of-the-art FPGA.