Bridging the Gap Between Neural Networks and Neuromorphic Hardware with A Neural Network Compiler

TL;DR

This paper introduces a compiler-based methodology that transforms trained neural networks into hardware-constrained versions, enabling efficient deployment on neuromorphic chips and PIM architectures with minimal accuracy loss.

Contribution

It presents a general compiler framework that adapts neural networks to hardware-specific restrictions, supporting both SNNs and ANNs, and demonstrates its effectiveness on real neuromorphic hardware.

Findings

Inference error is minimal after transformation.

Transformation time is much shorter than retraining.

Parameter sensitivity analysis reveals tradeoffs between accuracy and resource use.

Abstract

Different from developing neural networks (NNs) for general-purpose processors, the development for NN chips usually faces with some hardware-specific restrictions, such as limited precision of network signals and parameters, constrained computation scale, and limited types of non-linear functions. This paper proposes a general methodology to address the challenges. We decouple the NN applications from the target hardware by introducing a compiler that can transform an existing trained, unrestricted NN into an equivalent network that meets the given hardware's constraints. We propose multiple techniques to make the transformation adaptable to different kinds of NN chips, and reliable for restrict hardware constraints. We have built such a software tool that supports both spiking neural networks (SNNs) and traditional artificial neural networks (ANNs). We have demonstrated its effectiveness with a fabricated neuromorphic chip and a processing-in-memory (PIM) design. Tests show that the inference error caused by this solution is insignificant and the transformation time is much shorter than the retraining time. Also, we have studied the parameter-sensitivity evaluations to explore the tradeoffs between network error and resource utilization for different transformation strategies, which could provide insights for co-design optimization of neuromorphic hardware and software.