Auto-Generation of Pipelined Hardware Designs for Polar Encoder

TL;DR

This paper introduces a flexible framework and compiler for automatically generating pipelined polar encoder hardware architectures, enabling design space exploration and optimization for FPGA or ASIC implementations.

Contribution

It presents a novel general formula and an auto-generator tool for designing polar encoders with customizable code length and parallelism levels.

Findings

The auto-generator efficiently produces RTL descriptions for polar encoders.

Experimental results show the framework's effectiveness in hardware design.

The approach facilitates trade-offs between cost and performance.

Abstract

This paper presents a general framework for auto-generation of pipelined polar encoder architectures. The proposed framework could be well represented by a general formula. Given arbitrary code length $N$ and the level of parallelism $M$, the formula could specify the corresponding hardware architecture. We have written a compiler which could read the formula and then automatically generate its register-transfer level (RTL) description suitable for FPGA or ASIC implementation. With this hardware generation system, one could explore the design space and make a trade-off between cost and performance. Our experimental results have demonstrated the efficiency of this auto-generator for polar encoder architectures.