Suppressing Kirkendall Void Density in Circuit Interconnections by Strain Annealing

TL;DR

This paper introduces a strain-anneal technique to reduce Kirkendall void formation in circuit interconnections by controlling grain size and impurity removal, improving reliability in high-performance electronics.

Contribution

The study presents a novel strain-anneal method that effectively decreases void density by tailoring grain size and impurity content in copper substrates.

Findings

Increased grain size correlates with lower void density.

High annealing temperature recrystallization increases porosity and void sensitivity.

Impurity removal combined with grain growth reduces void formation.

Abstract

Unpredictable Kirkendall void formation at the interface of circuit interconnections underlies degradation in electronics, yet there is a lack of effective approaches to curb the amount of these voids. Here we developed a strain-anneal method to tailor grain size distributions in the copper substrate of interconnections, and demonstrate quantitatively that not only the removal of the impurities but also an increase in the grain size of the substrates leads to an appreciable decline in the void density. The interconnections on the substrate recrystallized at a high annealing temperature show the massive porosity and the increased sensitivity of the voiding to the grain size. Our findings have broad implications for manipulation of void propensity in many other hetero-interfaces and are essential for high-performance circuit bonding in high temperature/high power electronic devices based on wide band gap semiconductors.