HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA
Andreas Kurth, Pirmin Vogel, Alessandro Capotondi, Andrea Marongiu,, Luca Benini

TL;DR
HERO is an FPGA-based platform enabling rapid prototyping and exploration of heterogeneous embedded systems combining RISC-V cores and ARM processors, supporting software and hardware modifications with comprehensive tools.
Contribution
This work introduces HERO, a scalable, configurable FPGA platform integrating RISC-V PMCA clusters with an ARM Cortex-A processor, along with a complete software stack for research.
Findings
HERO supports flexible hardware configurations and modifications.
The platform enables detailed runtime analysis and testing.
Case studies demonstrate its effectiveness for research.
Abstract
Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host processor with programmable manycore accelerators (PMCAs) to combine general-purpose computing with domain-specific, efficient processing capabilities. While leading companies successfully advance their HESoC products, research lags behind due to the challenges of building a prototyping platform that unites an industry-standard host processor with an open research PMCA architecture. In this work we introduce HERO, an FPGA-based research platform that combines a PMCA composed of clusters of RISC-V cores, implemented as soft cores on an FPGA fabric, with a hard ARM Cortex-A multicore host processor. The PMCA architecture mapped on the FPGA is silicon-proven, scalable, configurable, and fully modifiable. HERO includes a complete software stack that consists of a heterogeneous cross-compilation toolchain with…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Interconnection Networks and Systems · Embedded Systems Design Techniques
