Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapse

TL;DR

This paper addresses the challenge of asymmetric nonlinear weight updates in hardware neural networks with analog resistive synapses by proposing co-optimized solutions that improve training accuracy on MNIST.

Contribution

It introduces new methods for engineering activation functions and threshold schemes to suppress training noise caused by nonlinear weight updates.

Findings

Achieved 87.8% accuracy with 6-bit synapses

Achieved 94.8% accuracy with 8-bit synapses

Successfully trained a two-layer perceptron online

Abstract

Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit dataset to 87.8/94.8% by using 6-bit/8-bit analog synapses, respectively, with extremely high asymmetric nonlinearity.