Weighted p-bits for FPGA implementation of probabilistic circuits

TL;DR

This paper introduces a scalable FPGA implementation of weighted probabilistic p-bits that can be used to construct invertible probabilistic circuits for solving complex problems like Subset Sum.

Contribution

It presents a novel FPGA-based design of weighted p-bits and a generalized tile architecture enabling diverse problem mappings, including invertible Boolean logic.

Findings

Successful hardware implementation of weighted p-bits on FPGA

Demonstration of solving Subset Sum problem in hardware

Potential for scalable probabilistic circuit applications

Abstract

Probabilistic spin logic (PSL) is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits (p-bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve problems of optimization, inference and also to implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this paper we present a scalable FPGA implementation of such invertible p-circuits. We implement a "weighted" p-bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p-bits to which a large class of problems beyond invertible Boolean logic can be mapped, and how invertibility can be applied to interesting problems such as the NP-complete Subset Sum Problem by solving a small instance of this problem in hardware.