FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability

TL;DR

This paper presents a novel FPGA design methodology in 130nm CMOS that enhances routability and robustness, utilizing open-source CAD tools and a Chisel model for rapid verification and deployment.

Contribution

It introduces an FPGA architecture with improved routability and robustness, supported by an open-source CAD flow and a Chisel-based verification model.

Findings

Successful FPGA implementation in 130nm CMOS with improved routability.

Validated architecture and bitstream through custom hardware and tools.

Demonstrated robustness across various resource utilizations and clock speeds.

Abstract

This paper outlines an FPGA VLSI design methodology that was used to realize a fully functioning FPGA chip in 130nm CMOS with improved routability and memory robustness. The architectural design space exploration and synthesis capability were enabled by the Verilog-to-Routing CAD tool. The capabilities of this tool were extended to enable bitstream generation and deployment. To validate the architecture and bitstream implementation, a Chisel (Constructing Hardware in the Embedded Scala Language) model of the FPGA was created to rapidly verify the microarchitectural details of the device prior to schematic design. A custom carrier board and configuration tool were used to verify correct operational characteristics of the FPGA over various resource utilizations and clock frequencies.