Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation
Sourav Dutta, Odysseas Zografos, Surya Gurunarayanan, Iuliana Radu,, Bart Soree, Francky Catthoor, Azad Naeemi

TL;DR
This paper introduces a nanoscale plasmonic majority gate that uses wave phase instead of intensity for computation, enabling non-Boolean logic and potential applications in real-time signal processing.
Contribution
It proposes a novel phase-based plasmonic majority gate with a cascadable design and a referencing scheme, advancing beyond traditional intensity-based plasmonic logic devices.
Findings
Demonstrates a 3-input plasmonic majority gate with 0.636 μm² area
Uses phase of surface-plasmon-polariton waves as the computational variable
Enables non-Boolean computation suitable for pattern recognition
Abstract
Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing…
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