Formal Verification of Probabilistic SystemC Models with Statistical Model Checking
Van Chan Ngo, Axel Legay

TL;DR
This paper presents a framework and implementation for applying Statistical Model Checking to large, probabilistic SystemC models, enabling efficient property verification without state space explosion.
Contribution
It introduces a novel framework for verifying probabilistic SystemC models using SMC, supporting timed, probabilistic, and user-defined properties with an automated tool.
Findings
Successful verification of large SystemC models using SMC
Support for user-defined primitives and fine-grained timing
Automated instrumentation and trace generation for SMC
Abstract
Transaction-level modeling with SystemC has been very successful in describing the behavior of embedded systems by providing high-level executable models, in which many of them have inherent probabilistic behaviors, e.g., random data and unreliable components. It thus is crucial to have both quantitative and qualitative analysis of the probabilities of system properties. Such analysis can be conducted by constructing a formal model of the system under verification and using Probabilistic Model Checking (PMC). However, this method is infeasible for large systems, due to the state space explosion. In this article, we demonstrate the successful use of Statistical Model Checking (SMC) to carry out such analysis directly from large SystemC models and allow designers to express a wide range of useful properties. The first contribution of this work is a framework to verify properties expressed…
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