Design Automation for Binarized Neural Networks: A Quantum Leap Opportunity?

TL;DR

This paper introduces a hardware design and synthesis method for ultra-low power Binarized Neural Networks (BNNs) that are purely combinational, enabling efficient near-sensor processing with significant reductions in area and energy consumption.

Contribution

It presents a novel combinational BNN design for ultra-low power processing, demonstrating substantial improvements in area and energy efficiency over existing methods.

Findings

Silicon area of 2.61mm2 for the combinational BNN

2.2x smaller area compared to reconfigurable networks

10x higher energy efficiency than comparable techniques

Abstract

Design automation in general, and in particular logic synthesis, can play a key role in enabling the design of application-specific Binarized Neural Networks (BNN). This paper presents the hardware design and synthesis of a purely combinational BNN for ultra-low power near-sensor processing. We leverage the major opportunities raised by BNN models, which consist mostly of logical bit-wise operations and integer counting and comparisons, for pushing ultra-low power deep learning circuits close to the sensor and coupling it with binarized mixed-signal image sensor data. We analyze area, power and energy metrics of BNNs synthesized as combinational networks. Our synthesis results in GlobalFoundries 22nm SOI technology shows a silicon area of 2.61mm2 for implementing a combinational BNN with 32x32 binary input sensor receptive field and weight parameters fixed at design time. This is 2.2x smaller than a synthesized network with re-configurable parameters. With respect to other comparable techniques for deep learning near-sensor processing, our approach features a 10x higher energy efficiency.