An 826 MOPS, 210 uW/MHz Unum ALU in 65 nm

TL;DR

This paper reports the first silicon implementation of a 128-bit unum floating-point arithmetic unit in 65 nm CMOS, achieving high speed and low power, demonstrating the practicality of unum formats in hardware.

Contribution

It introduces a silicon ASIC for unum floating-point arithmetic, including compression units, and provides measured performance and power metrics.

Findings

Achieves 413 MHz at 1.2 V in 65 nm CMOS

Power consumption of 210 uW/MHz

Supports addition and subtraction with compression features

Abstract

To overcome the limitations of conventional floating-point number formats, an interval arithmetic and variable-width storage format called universal number (unum) has been recently introduced. This paper presents the first (to the best of our knowledge) silicon implementation measurements of an application-specific integrated circuit (ASIC) for unum floating-point arithmetic. The designed chip includes a 128-bit wide unum arithmetic unit to execute additions and subtractions, while also supporting lossless (for intermediate results) and lossy (for external data movements) compression units to exploit the memory usage reduction potential of the unum format. Our chip, fabricated in a 65 nm CMOS process, achieves a maximum clock frequency of 413 MHz at 1.2 V with an average measured power of 210 uW/MHz.