Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint

TL;DR

This paper introduces a new hybrid BIST architecture and heuristic-based scheduling method for multi-clock domain SoCs, optimizing test time and power constraints, with experimental validation showing improved performance over prior approaches.

Contribution

It proposes a novel concurrent hybrid BIST architecture and a heuristic for core selection and test scheduling in multi-clock domain SoCs.

Findings

Optimized test scheduling reduces total test time.

Improved testing efficiency under power constraints.

Experimental results outperform previous methods.

Abstract

This paper presents a novel approach for test generation and test scheduling for multi-clock domain SoCs. A concurrent hybrid BIST architecture is proposed for testing cores. Furthermore, a heuristic for selecting cores to be tested concurrently and order of applying test patterns is proposed. Experimental results show that the proposed heuristics give us an optimized method for multi clock domain SoC testing in comparison with the previous works.