Enabling Fine-Grain Restricted Coset Coding Through Word-Level Compression for PCM

TL;DR

This paper introduces a novel encoding and compression technique for multi-level cell PCM that significantly reduces write energy, enhances endurance, and maintains reliability with minimal hardware overhead.

Contribution

It proposes a new word-level compression combined with restricted coset encoding at small data granularities, improving energy efficiency and endurance in PCM.

Findings

Reduces write energy by 39% on average at 16-bit granularity

Compresses over 91% of memory lines to store auxiliary data

Improves endurance by 20% and maintains reliability

Abstract

Phase change memory (PCM) has recently emerged as a promising technology to meet the fast growing demand for large capacity memory in computer systems, replacing DRAM that is impeded by physical limitations. Multi-level cell (MLC) PCM offers high density with low per-byte fabrication cost. However, despite many advantages, such as scalability and low leakage, the energy for programming intermediate states is considerably larger than programing single-level cell PCM. In this paper, we study encoding techniques to reduce write energy for MLC PCM when the encoding granularity is lowered below the typical cache line size. We observe that encoding data blocks at small granularity to reduce write energy actually increases the write energy because of the auxiliary encoding bits. We mitigate this adverse effect by 1) designing suitable codeword mappings that use fewer auxiliary bits and 2) proposing a new Word-Level Compression (WLC) which compresses more than 91% of the memory lines and provides enough room to store the auxiliary data using a novel restricted coset encoding applied at small data block granularities. Experimental results show that the proposed encoding at 16-bit data granularity reduces the write energy by 39%, on average, versus the leading encoding approach for write energy reduction. Furthermore, it improves endurance by 20% and is more reliable than the leading approach. Hardware synthesis evaluation shows that the proposed encoding can be implemented on-chip with only a nominal area overhead.