Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation

TL;DR

This paper introduces a magnetostriction-assisted spintronic device that enhances the performance of all-spin logic devices by reducing delay and energy consumption through a novel heterostructure design and detailed simulation analysis.

Contribution

The paper presents a new heterostructure device combining magnets and piezoelectrics, improving ASL device performance with detailed physics modeling and SPICE simulation benchmarking.

Findings

21x shorter delay compared to traditional ASL devices

27x lower energy dissipation per bit in a 32-bit ALU

Maintains low voltage operation and non-volatility

Abstract

We propose a heterostructure device comprised of magnets and piezoelectrics that significantly improves the delay and the energy dissipation of an all-spin logic (ASL) device. This paper studies and models the physics of the device, illustrates its operation, and benchmarks its performance using SPICE simulations. We show that the proposed device maintains low voltage operation, non-reciprocity, non-volatility, cascadability, and thermal reliability of the original ASL device. Moreover, by utilizing the deterministic switching of a magnet from the saddle point of the energy profile, the device is more efficient in terms of energy and delay and is robust to thermal fluctuations. The results of simulations show that compared to ASL devices, the proposed device achieves 21x shorter delay and 27x lower energy dissipation per bit for a 32-bit arithmetic-logic unit (ALU).