BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding

TL;DR

This paper introduces a multistage BIST architecture using an irregular polynomial BILBO structure to significantly reduce test time for complex integrated circuits, especially in SoC testing.

Contribution

It proposes a novel multistage BIST approach with an asymmetric polynomial reseeding technique to enhance testing efficiency in complex ICs.

Findings

35% average reduction in test time on ISCAS-89 benchmarks

Improved test results due to IP-BILBO structure

Enhanced suitability for SoC testing environments

Abstract

By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the increase in complexity of circuits, keeps testing a challenging problem. Two important challenges in testing of digital circuits are test time and accessing the circuit under test (CUT) for testing. These challenges become even more important in complex system on chip (SoC) zone. This paper presents a multistage test strategy to be implemented on a BIST architecture for reducing test time of a simple core as solution for more global application of SoC testing strategy. This strategy implements its test pattern generation and output response analyzer in a BILBO architecture. The proposed method benefits from an irregular polynomial BILBO (IP-BILBO) structure to improve its test results. Experimental results on ISCAS-89 benchmark circuits show an average of 35% improvement in test time in proportion to pervious work.