A Full Duplex Transceiver with Reduced Hardware Complexity

TL;DR

This paper presents a low-complexity full duplex transceiver design that effectively cancels self-interference using simplified analog and digital techniques, enabling practical in-band full duplex wireless communication.

Contribution

It introduces a novel low-complexity transceiver architecture combining circulator-based RF cancellation with non-linear digital filtering, reducing hardware complexity for full duplex systems.

Findings

Achieves 90 dB self-interference cancellation

Uses simplified analog front-end with SDR platform

Demonstrates effective in-band full duplex operation

Abstract

For future wireless communication systems, full duplex is seen as a possible solution to the ever present spectrum shortage. The key aspect to enable In-Band Full Duplex (IBFD) is sufficient cancellation of the unavoidable Self-Interference (SI). In this work we evaluate the performance of a low complexity IBFD transceiver, including the required analog and digital interference cancellation techniques. The Radio Frequency Self- Interference Canceler (RFSIC) is based on the isolation of a circulator in combination with a vector modulator regenerating the interference signal, to destructively combine it with the received signal. On the digital side, a Digital Self-Interference Cancellation (DSIC) algorithm based on non-linear adaptive filtering is used. With the simplified analog front-end of a Software Defined Radio (SDR) platform, SI cancellation of 90 dB is achieved with the presence of a received signal.