A Compact CMOS Memristor Emulator Circuit and its Applications
Vishal Saxena

TL;DR
This paper presents a compact CMOS circuit that emulates ideal memristor behavior, enabling practical applications in neuromorphic computing and machine learning by bridging the gap between conceptual memristors and chip-scale implementation.
Contribution
A novel CMOS memristor emulator circuit is designed and simulated, capable of integration in standard CMOS technology for diverse computing applications.
Findings
Successfully emulated ideal memristor characteristics in CMOS circuit
Demonstrated application in maze solving using analog parallelism
Circuit can be fabricated with standard CMOS processes
Abstract
Conceptual memristors have recently gathered wider interest due to their diverse application in non-von Neumann computing, machine learning, neuromorphic computing, and chaotic circuits. We introduce a compact CMOS circuit that emulates idealized memristor characteristics and can bridge the gap between concepts to chip-scale realization by transcending device challenges. The CMOS memristor circuit embodies a two-terminal variable resistor whose resistance is controlled by the voltage applied across its terminals. The memristor 'state' is held in a capacitor that controls the resistor value. This work presents the design and simulation of the memristor emulation circuit, and applies it to a memcomputing application of maze solving using analog parallelism. Furthermore, the memristor emulator circuit can be designed and fabricated using standard commercial CMOS technologies and opens…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
