Decanting the Contribution of Instruction Types and Loop Structures in the Reuse of Traces

TL;DR

This paper investigates how different instruction types and loop structures affect trace reuse efficiency, revealing that selective reuse can maintain performance while reducing reuse table accesses.

Contribution

It provides a detailed analysis of the impact of instruction subsets and loop-based reuse on trace reuse performance, which was not thoroughly studied before.

Findings

Disabling reuse outside loops does not harm performance.

Most speedup is retained even when not reusing all instruction types.

Reuse table accesses decrease by 12% when outside loop reuse is disabled.

Abstract

Reuse has been proposed as a microarchitecture-level mechanism to reduce the amount of executed instructions, collapsing dependencies and freeing resources for other instructions. Previous works have used reuse domains such as memory accesses, integer or not floating point, based on the reusability rate. However, these works have not studied the specific contribution of reusing different subsets of instructions for performance. In this work, we analysed the sensitivity of trace reuse to instruction subsets, comparing their efficiency to their complementary subsets. We also studied the amount of reuse that can be extracted from loops. Our experiments show that disabling trace reuse outside loops does not harm performance but reduces in 12% the number of accesses to the reuse table. Our experiments with reuse subsets show that most of the speedup can be retained even when not reusing all types of instructions previously found in the reuse domain.