P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs

TL;DR

This paper presents a configurable FPGA-based architecture for high-speed, low-latency packet parsers in SDN networks, generated from P4 code, achieving 100 Gb/s data rate with reduced latency and resource usage.

Contribution

It introduces an open-source, P4-compatible high-level synthesis approach for FPGA-based packet parsers that significantly improves speed and efficiency.

Findings

Achieves 100 Gb/s data rate in FPGA

Reduces latency by 45%

LUT usage decreased by 40%

Abstract

Packet parsing is a key step in SDN-aware devices. Packet parsers in SDN networks need to be both reconfigurable and fast, to support the evolving network protocols and the increasing multi-gigabit data rates. The combination of packet processing languages with FPGAs seems to be the perfect match for these requirements. In this work, we develop an open-source FPGA-based configurable architecture for arbitrary packet parsing to be used in SDN networks. We generate low latency and high-speed streaming packet parsers directly from a packet processing program. Our architecture is pipelined and entirely modeled using templated C++ classes. The pipeline layout is derived from a parser graph that corresponds a P4 code after a series of graph transformation rounds. The RTL code is generated from the C++ description using Xilinx Vivado HLS and synthesized with Xilinx Vivado. Our architecture achieves 100 Gb/s data rate in a Xilinx Virtex-7 FPGA while reducing the latency by 45% and the LUT usage by 40% compared to the state-of-the-art.