Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS

TL;DR

This paper presents Hydra, a 65nm CMOS hardware accelerator for real-time, high-quality edge-aware permeability filtering in video processing, optimized for embedded systems with limited area and memory bandwidth.

Contribution

It introduces a tiled hardware implementation of the permeability filter that significantly reduces memory bandwidth and area, enabling real-time processing on embedded hardware.

Findings

Filters 720p video at 24.8 Hz

Achieves 6.7 GFLOPS/mm2 compute density

Reduces external memory bandwidth by 6.4x

Abstract

Many modern video processing pipelines rely on edge-aware (EA) filtering methods. However, recent high-quality methods are challenging to run in real-time on embedded hardware due to their computational load. To this end, we propose an area-efficient and real-time capable hardware implementation of a high quality EA method. In particular, we focus on the recently proposed permeability filter (PF) that delivers promising quality and performance in the domains of HDR tone mapping, disparity and optical flow estimation. We present an efficient hardware accelerator that implements a tiled variant of the PF with low on-chip memory requirements and a significantly reduced external memory bandwidth (6.4x w.r.t. the non-tiled PF). The design has been taped out in 65 nm CMOS technology, is able to filter 720p grayscale video at 24.8 Hz and achieves a high compute density of 6.7 GFLOPS/mm2 (12x higher than embedded GPUs when scaled to the same technology node). The low area and bandwidth requirements make the accelerator highly suitable for integration into SoCs where silicon area budget is constrained and external memory is typically a heavily contended resource.