Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

TL;DR

This paper presents the development of a comprehensive characterization and verification environment for the RD53A pixel readout chip in 65 nm CMOS, including a test system and simulation environment to ensure design robustness for HL-LHC upgrades.

Contribution

It introduces a modular test and data acquisition system and a dedicated simulation environment for the RD53A chip, facilitating extensive testing and validation.

Findings

Successful implementation of a modular data acquisition framework

Effective simulation environment for RD53A verification

Preparation for extensive chip testing at HL-LHC upgrades

Abstract

The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.