Timing Aware Dummy Metal Fill Methodology

TL;DR

This paper investigates the impact of dummy metal fill on circuit timing and proposes two novel approaches to mitigate this effect, leading to improved timing performance in integrated circuits.

Contribution

It introduces two timing-aware dummy metal fill methods that reduce parasitic coupling capacitance and improve circuit timing, which is a novel approach in metal fill design.

Findings

Significant reduction in parasitic coupling capacitance.

Improved timing performance over traditional methods.

Effective shielding using reference nets enhances circuit reliability.

Abstract

In this paper, we analyzed parasitic coupling capacitance coming from dummy metal fill and its impact on timing. Based on the modeling, we proposed two approaches to minimize the timing impact from dummy metal fill. The first approach applies more spacing between critical nets and metal fill, while the second approach leverages the shielding effects of reference nets. Experimental results show consistent improvement compared to traditional metal fill method.