The ALICE trigger system for LHC Run 3

TL;DR

The paper describes an upgraded, dead-time free ALICE trigger system for LHC Run 3, featuring new hardware, a high-speed trigger data transmission, and a versatile trigger board based on FPGA technology.

Contribution

It introduces a novel trigger system with a new TTC-PON architecture and a universal trigger board capable of dual functions, enhancing performance and flexibility for LHC Run 3.

Findings

Achieved dead time free operation

Enabled trigger data transmission at 9.6 Gbps

Developed a versatile trigger board based on FPGA

Abstract

The ALICE Central Trigger Processor (CTP) is going to be upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing Control (TTC-PON) system based on a Passive Optical Network (PON) system. The new trigger system has been designed as dead time free and able to transmit trigger data at 9.6 Gbps. A new universal trigger board has been designed, where by changing the FMC card, it can function as a CTP or as a LTU. It is based on the Xilinx Kintex Ultrascale FPGA and upgraded TTC-PON. The new trigger system and the prototype of the trigger board will be presented.