Non Uniform On Chip Power Delivery Network Synthesis Methodology

TL;DR

This paper introduces a non-uniform on-chip power delivery network synthesis methodology that optimizes PDN design for reduced congestion and IR safety, improving timing and power efficiency.

Contribution

It presents a novel congestion-driven, IR-guarded non-uniform PDN synthesis approach combining global and local optimization techniques.

Findings

Significant reduction in PDN length without IR/EM impact

Improved timing performance through optimized PDN design

Potential power savings demonstrated with the proposed methodology

Abstract

In this paper, we proposed a non-uniform power delivery network (PDN) synthesis methodology. It first constructs initial PDN using uniform approach. Then preliminary power integrity analysis is performed to derive IR-safe candidate window. Congestion map is obtained based global route congestion estimation. A self-adaptive non-uniform PDN synthesis is then performed to globally and locally optimize PDN over selected regions. The PDN synthesis is congestion-driven and IR- guarded. Experimental results show significant timing important in trade-off small PDN length reduction with no EM/IR impact. We further explored potential power savings using our non-uniform PDN synthesis methodology.