A Single-Channel Architecture for Algebraic Integer Based 8$\times$8 2-D DCT Computation

TL;DR

This paper presents a compact, area-efficient architecture for real-time 8x8 2-D DCT computation using algebraic integer encoding, reducing hardware complexity while maintaining exact results, suitable for high-speed image and video processing.

Contribution

It introduces a single-channel 2-D DCT architecture with an improved AI-based 1-D DCT algorithm, reducing hardware resources compared to previous multi-channel designs.

Findings

20% reduction in area compared to previous architectures

23% reduction in area-time complexity metrics

Achieves a maximum clock rate of 951 MHz in CMOS implementation

Abstract

An area efficient row-parallel architecture is proposed for the real-time implementation of bivariate algebraic integer (AI) encoded 2-D discrete cosine transform (DCT) for image and video processing. The proposed architecture computes 8$\times$8 2-D DCT transform based on the Arai DCT algorithm. An improved fast algorithm for AI based 1-D DCT computation is proposed along with a single channel 2-D DCT architecture. The design improves on the 4-channel AI DCT architecture that was published recently by reducing the number of integer channels to one and the number of 8-point 1-D DCT cores from 5 down to 2. The architecture offers exact computation of 8$\times$8 blocks of the 2-D DCT coefficients up to the FRS, which converts the coefficients from the AI representation to fixed-point format using the method of expansion factors. Prototype circuits corresponding to FRS blocks based on two expansion factors are realized, tested, and verified on FPGA-chip, using a Xilinx Virtex-6 XC6VLX240T device. Post place-and-route results show a 20% reduction in terms of area compared to the 2-D DCT architecture requiring five 1-D AI cores. The area-time and area-time${}^2$ complexity metrics are also reduced by 23% and 22% respectively for designs with 8-bit input word length. The digital realizations are simulated up to place and route for ASICs using 45 nm CMOS standard cells. The maximum estimated clock rate is 951 MHz for the CMOS realizations indicating 7.608$\cdot$10$^9$ pixels/seconds and a 8$\times$8 block rate of 118.875 MHz.