A software framework for pipelined arithmetic algorithms in field programmable gate arrays

TL;DR

This paper introduces a C++ software framework that automates the simulation and HDL code generation for pipelined arithmetic algorithms in FPGAs, streamlining development for high energy physics hardware triggers.

Contribution

The framework simplifies FPGA algorithm development by integrating simulation and HDL code generation in C++, reducing manual effort and potential errors.

Findings

Automates simulation of pipelined algorithms

Generates HDL code from C++ descriptions

Facilitates rapid development of FPGA hardware triggers

Abstract

Pipelined algorithms implemented in field programmable gate arrays are being extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms are increases rapidly. For development of such hardware triggers, algorithms are developed in $\texttt{C++}$, ported to hardware description language for synthesizing firmware, and then ported back to $\texttt{C++}$ for simulating the firmware response down to the single bit level. We present a $\texttt{C++}$ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.