Faster Carry Bit Computation for Adder Circuits with Prescribed Arrival Times

TL;DR

This paper introduces an algorithm for constructing the fastest Boolean circuits for carry bit computation in binary addition with prescribed input arrival times, optimizing delay based on input timing constraints.

Contribution

It provides the fastest known algorithm for designing extit{and/or} formulas with given arrival times, improving delay bounds for carry computation and adder circuits.

Findings

Maximum delay is bounded by log_2 W + log_2 log_2 m + log_2 log_2 log_2 m + 4.3.

The method achieves optimal or near-optimal delay bounds for extit{and/or} formulas.

It yields the fastest circuits for carry computation and addition in terms of delay.

Abstract

We consider the fundamental problem of constructing fast circuits for the carry bit computation in binary addition. Up to a small additive constant, the carry bit computation reduces to computing an \aop, i.e., a formula of type $t_0 \land (t_1 \lor (t_2 \land ( \dots t_{m-1}) \dots )$ or $t_0 \lor (t_1 \land (t_2 \lor ( \dots t_{m-1}) \dots )$. We present an algorithm that computes the fastest known Boolean circuit for an \aop~ with given arrival times $a(t_0), \dotsc, a(t_{m-1})$ for the input signals. Our objective function is delay, a natural generalization of depth with respect to arrival times. The maximum delay of the circuit we compute is $\log_2 W + \log_2 \log_2 m + \log_2 \log_2 \log_2 m + 4.3$, where $W := \sum_{i = 0}^{m-1} 2^{a(t_i)}$. Note that $\lceil \log_2 W \rceil$ is a lower bound on the delay of any circuit depending on inputs $t_0, \dotsc, t_{m-1}$ with prescribed arrival times. Our method yields the fastest circuits for \aop s, carry bit computation and adders in terms of delay known so far.