A Multi-Bit Neuromorphic Weight Cell using Ferroelectric FETs, suitable for SoC Integration

TL;DR

This paper introduces a multi-bit neuromorphic weight cell using ferroelectric FETs that enables high-performance, inference-only accelerators with non-volatile, purely digital weight storage and efficient multiply-accumulate operations.

Contribution

It presents a novel, simple, and purely digital multi-bit weight cell design using FeFETs for neuromorphic accelerators, emphasizing high linearity and large ON/OFF ratio.

Findings

Achieves non-volatile digital weight storage with FeFETs.

Demonstrates high linearity and large ON/OFF ratio in the weight cell.

Analyzes key performance tradeoffs and device requirements.

Abstract

A multi-bit digital weight cell for high-performance, inference-only non-GPU-like neuromorphic accelerators is presented. The cell is designed with simplicity of peripheral circuitry in mind. Non-volatile storage of weights which eliminates the need for DRAM access is based on FeFETs and is purely digital. The Multiply-and-Accumulate operation is performed using passive resistors, gated by FeFETs. The resulting weight cell offers a high degree of linearity and a large ON/OFF ratio. The key performance tradeoffs are investigated, and the device requirements are elucidated.