High Performance Canny Edge Detector using Parallel Patterns for Scalability on Modern Multicore Processors

TL;DR

This paper presents a high-performance, scalable implementation of the Canny Edge Detector utilizing parallel patterns to leverage multicore processors, significantly improving efficiency in image processing tasks.

Contribution

It introduces a novel parallel pattern-based approach for Canny Edge Detection that enhances scalability and performance on modern multicore architectures.

Findings

Significant performance improvements over traditional implementations

Effective utilization of multicore resources

Scales well with increasing core counts

Abstract

Canny Edge Detector (CED) is an edge detection operator commonly used by most Image Feature Extraction (IFE) Algorithms and Image Processing Applications. This operator involves the use of a multi-stage algorithm to detect edges in a wide range of images. Edge detection is at the forefront of image processing and hence, it is crucial to have at an up to scale level. Multicore Processors have emerged as the next solution for tackling compute intensive tasks that have a high demand for computational power. Having significant changes that restructured the microprocessor industry, it is evident that the best way to promote efficiency and improve performance is no longer by increasing the clock speeds on traditional monolithic processors but by adopting and utilizing Processors with Multicore architectures. In this paper we provide a high performance implementation of Canny Edge Detector using parallel patterns for improved performance and Scalability on Multicore Processors. The results show significant improvements in overall performance and this proves that our implementation using parallel patterns does not under utilize resources but scales well for multicore processors.