The Semantics of Transactions and Weak Memory in x86, Power, ARM, and C++

TL;DR

This paper explores how transactional memory interacts with weak memory models in architectures like x86, Power, ARM, and C++, providing formal models and tooling to understand their combined semantics and implications.

Contribution

It extends existing weak memory models with rules for transactional memory and offers automated tools for validation and analysis of TM-related transformations.

Findings

ARMv8 TM extension conflicts with lock elision

Models enable validation against hardware implementations

Tools support analysis of TM transformations

Abstract

Weak memory models provide a complex, system-centric semantics for concurrent programs, while transactional memory (TM) provides a simpler, programmer-centric semantics. Both have been studied in detail, but their combined semantics is not well understood. This is problematic because such widely-used architectures and languages as x86, Power, and C++ all support TM, and all have weak memory models. Our work aims to clarify the interplay between weak memory and TM by extending existing axiomatic weak memory models (x86, Power, ARMv8, and C++) with new rules for TM. Our formal models are backed by automated tooling that enables (1) the synthesis of tests for validating our models against existing implementations and (2) the model-checking of TM-related transformations, such as lock elision and compiling C++ transactions to hardware. A key finding is that a proposed TM extension to ARMv8 currently being considered within ARM Research is incompatible with lock elision without sacrificing portability or performance.