Validation of hardware events for successful performance pattern identification in High Performance Computing

TL;DR

This paper defines and validates hardware event sets on Intel Haswell to improve performance pattern detection in HPC, addressing hardware limitations and ensuring reliable identification of performance issues.

Contribution

It introduces specific HPM event sets for performance pattern detection in HPC and validates their accuracy on Intel Haswell processors.

Findings

Validated event sets for pattern detection are accurate.

Identified hardware limitations affecting pattern recognition.

Provided guidelines for reliable performance analysis in HPC.

Abstract

Hardware performance monitoring (HPM) is a crucial ingredient of performance analysis tools. While there are interfaces like LIKWID, PAPI or the kernel interface perf\_event which provide HPM access with some additional features, many higher level tools combine event counts with results retrieved from other sources like function call traces to derive (semi-)automatic performance advice. However, although HPM is available for x86 systems since the early 90s, only a small subset of the HPM features is used in practice. Performance patterns provide a more comprehensive approach, enabling the identification of various performance-limiting effects. Patterns address issues like bandwidth saturation, load imbalance, non-local data access in ccNUMA systems, or false sharing of cache lines. This work defines HPM event sets that are best suited to identify a selection of performance patterns on the Intel Haswell processor. We validate the chosen event sets for accuracy in order to arrive at a reliable pattern detection mechanism and point out shortcomings that cannot be easily circumvented due to bugs or limitations in the hardware.