FPGA based Parallelized Architecture of Efficient Graph based Image Segmentation Algorithm
Roopal Nahar, Akanksha Baranwal, K.Madhava Krishna

TL;DR
This paper presents FPGA-based parallel architectures for an efficient graph-based image segmentation algorithm, significantly improving speed and power efficiency for real-time applications in mobile robotics.
Contribution
It introduces three novel FPGA architectures for the graph-based segmentation algorithm, achieving at least 2X speedup and lower power consumption compared to software implementations.
Findings
Achieved at least 2X speed gain over existing implementations.
Optimized for low power consumption and real-time processing.
Enabled deployment on mobile robotic systems.
Abstract
Efficient and real time segmentation of color images has a variety of importance in many fields of computer vision such as image compression, medical imaging, mapping and autonomous navigation. Being one of the most computationally expensive operation, it is usually done through software imple- mentation using high-performance processors. In robotic systems, however, with the constrained platform dimensions and the need for portability, low power consumption and simultaneously the need for real time image segmentation, we envision hardware parallelism as the way forward to achieve higher acceleration. Field-programmable gate arrays (FPGAs) are among the best suited for this task as they provide high computing power in a small physical area. They exceed the computing speed of software based implementations by breaking the paradigm of sequential execution and accomplishing more per clock…
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Taxonomy
MethodsSPEED: Separable Pyramidal Pooling EncodEr-Decoder for Real-Time Monocular Depth Estimation on Low-Resource Settings
