Low-Energy Deep Belief Networks using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons

TL;DR

This paper presents a low-energy hardware implementation of deep belief networks using spintronic probabilistic neurons with intrinsic sigmoidal activation, validated through device, circuit, and application-level simulations on the MNIST dataset.

Contribution

It introduces a novel spintronic probabilistic neuron model for low-energy deep belief networks and demonstrates its effectiveness in digit recognition tasks.

Findings

Achieved a reduction in error rate from 36.8% to 3.7% with larger networks and training data.

Validated the sigmoidal behavior of p-bits through device-level physics simulations.

Analyzed power, area, and accuracy tradeoffs in probabilistic spintronic neural networks.

Abstract

A low-energy hardware implementation of deep belief network (DBN) architecture is developed using near-zero energy barrier probabilistic spin logic devices (p-bits), which are modeled to realize an intrinsic sigmoidal activation function. A CMOS/spin based weighted array structure is designed to implement a restricted Boltzmann machine (RBM). Device-level simulations based on precise physics relations are used to validate the sigmoidal relation between the output probability of a p-bit and its input currents. Characteristics of the resistive networks and p-bits are modeled in SPICE to perform a circuit-level simulation investigating the performance, area, and power consumption tradeoffs of the weighted array. In the application-level simulation, a DBN is implemented in MATLAB for digit recognition using the extracted device and circuit behavioral models. The MNIST data set is used to assess the accuracy of the DBN using 5,000 training images for five distinct network topologies. The results indicate that a baseline error rate of 36.8% for a 784x10 DBN trained by 100 samples can be reduced to only 3.7% using a 784x800x800x10 DBN trained by 5,000 input samples. Finally, Power dissipation and accuracy tradeoffs for probabilistic computing mechanisms using resistive devices are identified.