Thread-Modular Static Analysis for Relaxed Memory Models

TL;DR

This paper introduces a static analysis method tailored for concurrent software on weak memory models, improving accuracy by efficiently checking interference feasibility to reduce false alarms.

Contribution

It presents a unified, Datalog-based framework for interference feasibility analysis that enhances static analysis precision on weak memory models.

Findings

Significantly reduces false alarms in static analysis.

Outperforms existing techniques in accuracy.

Maintains moderate runtime overhead.

Abstract

We propose a memory-model-aware static program analysis method for accurately analyzing the behavior of concurrent software running on processors with weak consistency models such as x86-TSO, SPARC-PSO, and SPARC-RMO. At the center of our method is a unified framework for deciding the feasibility of inter-thread interferences to avoid propagating spurious data flows during static analysis and thus boost the performance of the static analyzer. We formulate the checking of interference feasibility as a set of Datalog rules which are both efficiently solvable and general enough to capture a range of hardware-level memory models. Compared to existing techniques, our method can significantly reduce the number of bogus alarms as well as unsound proofs. We implemented the method and evaluated it on a large set of multithreaded C programs. Our experiments showthe method significantly outperforms state-of-the-art techniques in terms of accuracy with only moderate run-time overhead.